The present invention generally relates to spacers for FETs (Field Effect Transistors) and more particularly to the formation of a recessed source/drain strap for a MUGFET (Multi-Gate FET).
As the end of linear scaling of planar complementary metal oxide semiconductors (CMOS) approaches, alternative device structures are being evaluated. One of the primary candidates is FINFET (Fin Field Effect Transistor) technology, where a thin fin, or pillar of silicon is created using sub-lithographic techniques, thereby allowing placement of the gate on sides of the fin, which in the “on” state, fully depletes the silicon in the fin, making it a high performance device.
The term FINFET generally refers to a nonplanar, double-gate transistor. Integrated circuits that include INFETs may be fabricated on a bulk silicon substrate or, more commonly, on a silicon-on-insulator (SOI) wafer that includes an active SOI layer of a single crystal semiconductor, such as silicon, a substrate, and a buried insulator layer, e.g., a buried oxide layer that separates and electrically isolates the substrate from the semiconductor layer. Each FINFET generally includes a narrow vertical fin body of single crystal semiconductor material with vertically-projecting sidewalls. A gate contact or electrode intersects a channel region of the fin body and is isolated electrically from the fin body by a thin gate dielectric layer. At opposite ends of the fin body are heavily-doped source/drain regions.
A multi-gate device or Multi-gate Field Effect Transistor (MUGFET) refers to a MOSFET that incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes.
In a multi-gate device, the channel is surrounded by several gates on multiple surfaces, allowing more effective suppression of “off-state” leakage current. Multiple gates also allow enhanced current in the “on” state, also known as drive current. These advantages translate to lower power consumption and enhanced device performance. Nonplanar devices are also more compact than conventional planar transistors, enabling higher transistor density, which translates to smaller overall microelectronics.
In a conventional fabrication process of a MUGFET, it is desirable to provide for electrical connection to one or more fins from a wiring level to the transistor. In particular, such connections are prone to the introduction of added (series) resistances to source and drain as well as added parasitic capacitance from gate to source and gate to drain. It is, therefore, further desirable to provide electrical connections to one or more fins in a manner that introduces minimal added series resistance and minimal added gate-to-source and gate-to-drain capacitances. A large contact area of metal silicide to highly doped regions (source and drain) of the fins is needed to attain low resistance; prior-art structures introduced to add such area have also added significantly to the capacitance between the gate and the low-resistance structures.
The purpose of the strap is to form a conductive region between the FINFETs that is both low in resistance and low in capacitance. A conductive strap recessed below the surface plane of the FINFETs limits the capacitance between the conductive strap and the gate at very low levels. A conductive strap that is planar with the fins (that shorts the ends together) has a very high capacitance to the gate region. This gate to strap capacitance results in a switching speed delay and higher power.